VHDL for Logic Synthesis

VHDL for Logic Synthesis

by Andrew Rushton
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This is the first book to detail the use of VHDL with logic synthesis techniques, showing how to use the hardware description language to achieve SLSI design results.

It explains VHDL features in terms of the hardware mappings performed in synthesis basic.

First published
2011
Publishers
Wiley & Sons· Incorporated· John
Language
English

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